|Title:||Fault masking in synchronous and in asynchronous logic - a comparsion||Other Titles:||Fehlermaskierung in Asynchroner Logik||Language:||English||Authors:||Ramsl, Wolfgang||Qualification level:||Diploma||Advisor:||Steininger, Andreas||Assisting Advisor:||Najvirt, Robert||Issue Date:||2019||Citation:||
Ramsl, W. (2019). Fault masking in synchronous and in asynchronous logic - a comparsion [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2019.25573
|Number of Pages:||73||Qualification level:||Diploma||Abstract:||
The topic of this diploma thesis is the investigation of fault masking effects in synchronous and asynchronous logic. A fault is said to be masked if it affects a circuit but never creates an erroneous state and hence stays ineffective. In synchronous logic it is known that faults can be masked on three different levels: (1) Electrical masking: A fault is injected on the electrical level, but it doesnt affect the logical level. The current pulse induced is not large enough to change the boolean value. (2) Logical masking: The fault changes a boolean value but the logical function which is performed on this signal does not take it into account. For example if you look at an AND-Gate (2 inputs), a „false“ logic 1 only propagates if the other input is also 1. This we call implicit logical masking. Explicit logical masking is related to majority voting with replicated functions. (3) Temporal (latching-window) masking: This level deals with the temporal behavior, the fault disturbs a signal but it isnt captured. For example a transient fault between two clock edges in a synchronous circuit has no effect on the storage element as long as its effect has vanished by the next clock event. While (1) and (2) work similarly in synchronous and asynchronous logic, temporal masking (3) will be different. Instead of the rigid clock in synchronous logic there is a flexible timing driven by completion detection. The consideration of skew effects will be one focus of this thesis, whose general aim is to investigate the masking effects in both theory and practice. The result of the diploma thesis is expected to be a model which explains the behavior of masking effects on the three different levels. With the help of this model the appearance of faults and the bevaviour of masking effects in synchronous and asynchronous logic should be better understood. We will get a (also quantitative) comparison between masking effects in synchronous and asynchronous logic because those effects are already investigated in synchronous logic.
|Keywords:||asynchronous logic; synchronous logic; pipeline; transient faults||URI:||https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-129778
|DOI:||10.34726/hss.2019.25573||Library ID:||AC15485485||Organisation:||E182 - Institut für Technische Informatik||Publication Type:||Thesis
|Appears in Collections:||Thesis|
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