Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles

Abstract

Asynchronous circuits, specifically those using a quasi delay-insensitive (QDI) implementation are known for their high resilience against timing uncertainties. However, their event-based operation principle impedes their temporal masking capability, making them more susceptible to fault-induced transitions caused by single event transients. While synchronous circuits obtain high resilience through temporal masking that is established through the sampling of data by flip flops, asynchronous circuits, by design must be flexible about the phases of data validity leaving a larger attack surface for faults. Consequently, previous work has proposed to narrow down the windows in which data changes are accepted, in order to improve the temporal masking in QDI designs.In this paper, we analyze the fault sensitivity of asynchronous QDI circuits when subjected to single event transients. We do so by performing extensive fault injection experiments into different buffer styles to identify parameters that are the main contributors to the fault sensitivity of the circuit and compare their resilience.For that purpose, we use two variants of a multiplier circuit as target circuits. One with the shift and add operations arranged in a linear pipeline, and another one with an internal ring structure that computes the result iteratively, yielding designs with the same logic and buffer implementations, yet very different modes of operation. By varying the buffer styles, we are able to show the difference in robustness as well as the effectiveness of fault mitigation techniques inherent in some buffer styles.