Identification and Confinement of Fault Sensitivity Windows in QDI Logic

Abstract

Asynchronous, specifically QDI circuits are known to exhibit high resilience against faults affecting the timing. At the same time, their event based operation principle makes them susceptible to glitches. While synchronous circuits obtain high resilience through temporal masking that is established through the sampling of data by flip flops, asynchronous designs, by trying to be flexible about the phases of data validity, often have lower masking capabilities. Consequently, previous work has proposed to narrow down the windows in which data changes are accepted, in order to improve the temporal masking in QDI designs. In this paper we study the natural resilience of different QDI templates in more detail and quantitatively determine the windows of vulnerability through extensive fault injection experiments in simulation. To this end we propose a novel way of visualizing and analyzing the sensitivity windows that aids in identifying the key dependencies and vulnerabilities. In addition we introduce and evaluate two low-cost extensions for the pipeline registers which allow either to stall the operation in case a glitch creates an illegal symbol, or to prevent the creation of an illegal symbol in the first place.