Hierarchical multipliers: A framework for high-speed multiple error detecting architectures

Abstract

The demand for high-performance and reliable processing systems is steadily increasing, also in applications where multiple transient faults may occur. As multipliers are one of the main building blocks of the processing systems, employing a cost-efficient and high-speed method handling multiple-errors is of great importance. In this paper, at first a framework to achieve multiple error detection in the multipliers is proposed, which is entirely independent of the multiplier type and error detection method. Then, the self-checking hierarchical multipliers with multiple error detection capability up to the size of 64 × 64 bits are proposed in such a way that the low-cost and high-speed designs are achieved with high multiple error detection probabilities. Experimental results based on analysis and simulation show that the proposed 32 × 32 and 64 × 64 multipliers based on each of Dadda or Braum structures as high-speed parallel and array multipliers, respectively, achieve more than 99.8% error detection probability against three or more simultaneous errors. This capability for 64 × 64 multipliers is attained with 35% area overhead and less than 5% delay overhead compared to the basic non-self-checking design.