Dervic, A., & Zimmermann, H. (2022). SPAD Mixed-Quenching Circuit in 0.35-µm CMOS for Achieving a PDP of 39.2% at 854 nm. In Institute of Electrical and Electronics Engineers (Ed.), 2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES 2022) (pp. 116–119). IEEE Xplore. https://doi.org/10.23919/MIXDES55591.2022.9838232
This paper presents a fully-integrated optical sensor with SPAD and mixed quenching/resetting circuit with sensing stage based on a tunable-threshold inverter optimized for the standard 0.35-µm CMOS technology. The presented quencher features a controllable detection threshold voltage and an adjustable total dead time. The quenching circuit 5QC achieves 16.5 V excess bias voltage (five times the supply voltage). The dead time ranges from 7.5 ns to 51.5 ns, which corresponds to a saturation count rate range from 19.4 Mcps to 133.3 Mcps. The quencher is optimized for SPADs with a capacitance ranging from 50 fF up to 400 fF. Using our published measured photon detection probability (PDP) results and extrapolating them, a peak PDP of 75.6% at 652 nm and a PDP of 39.2% at 854 nm is estimated for VEX = 16.5 V. To the authors' best knowledge, the presented PDP result has never been reached before for a fully-integrated SPAD sensor in standard CMOS technology.
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Project title:
SPAD-basierte faser-optische CMOS Empfänger: P 28335-N30 (Fonds zur Förderung der wissenschaftlichen Forschung (FWF))
