Automatic Grid Refinement for Thin Material Layer Etching in Process TCAD Simulations

Abstract

Thin material layers are common structures in modern semiconductor device fabrication and are particularly necessary for light-emitting diodes and three-dimensional NAND memory devices. Such layers are not only deposited on the flat wafer surface but are also partially removed during subsequent etching steps. Level-set based process TCAD simulations are capable of representing flat thin material layers, such as those occurring after deposition, with sub-grid accuracy. However, topographical changes during etching processes modeled via Boolean operations expose the low underlying grid resolution, leading to detrimental artifacts. We present a novel algorithm that analyzes the thickness of all material layers and derives a refined target resolution for local regions of thin layers affected by the etching process. This allows to accurately represent topographical changes in thin layers by hierarchically refining the grid without unnecessary refinement in unaffected regions of the domain. We simulate the fabrication of a light-emitting diode device using our algorithm to automatically predict the optimal resolution for all etched material layers. Our algorithm selects efficient refinement factors to obtain the local target resolutions of the hierarchical grids, and achieves a three times faster computation time than a benchmark refinement algorithm based on topographical features.