Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Chattopadhyay, Saranyu; Lonsing, Florian; Piccolboni, Luca; Soni, Deepraj; Wei, Peng; Zhang, Xiaofan; Zhou, Yuan; Carloni, Luca; Chen, Deming; Cong, Jason; Karri, Ramesh; Zhang, Zhiru; Trippel, Caroline; Barrett, Clark; Mitra, Subhasish

doi:10.34727/2021/isbn.978-3-85448-046-4_12

Title:	Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition
Authors:	Chattopadhyay, Saranyu Lonsing, Florian Piccolboni, Luca Soni, Deepraj Wei, Peng Zhang, Xiaofan Zhou, Yuan Carloni, Luca Chen, Deming Cong, Jason Karri, Ramesh Zhang, Zhiru Trippel, Caroline Barrett, Clark Mitra, Subhasish
Issue Date:	Oct-2021
Citation:	Chattopadhyay, S., Lonsing, F., Piccolboni, L., Soni, D., Wei, P., Zhang, X., Zhou, Y., Carloni, L., Chen, D., Cong, J., Karri, R., Zhang, Z., Trippel, C., Barrett, C., & Mitra, S. (2021). Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. In Proceedings of the 21st Conference on Formal Methods in Computer-Aided Design – FMCAD 2021 (pp. 42–52). TU Wien Academic Press. https://doi.org/10.34727/2021/isbn.978-3-85448-046-4_12
Book Title:	Proceedings of the 21st Conference on Formal Methods in Computer-Aided Design – FMCAD 2021
Series:	Conference Series: Formal Methods in Computer-Aided Design
Keywords:	formal methods formale Methode
URI:	http://hdl.handle.net/20.500.12708/18628 https://doi.org/10.34727/2021/isbn.978-3-85448-046-4_12
DOI:	10.34727/2021/isbn.978-3-85448-046-4_12
Book DOI:	10.34727/2021/isbn.978-3-85448-046-4
License:	CC BY 4.0
Publication Type:	Inproceedings Konferenzbeitrag
Appears in Collections:	Open Access Series Conference Paper