Kokologiannakis, M., Ren, X., & Vafeiadis, V. (2021). Dynamic Partial Order Reductions for Spinloops. In Proceedings of the 21st Conference on Formal Methods in Computer-Aided Design – FMCAD 2021 (pp. 163–172). TU Wien Academic Press. https://doi.org/10.34727/2021/isbn.978-3-85448-046-4_25
E192-04 - Forschungsbereich Formal Methods in Systems Engineering
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Series:
Conference Series: Formal Methods in Computer-Aided Design
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Published in:
Proceedings of the 21st Conference on Formal Methods in Computer-Aided Design – FMCAD 2021
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Date (published):
Oct-2021
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Number of Pages:
10
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Publisher:
TU Wien Academic Press, Wien
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Peer reviewed:
Yes
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Keywords:
stateless model checking; spinloops
en
Abstract:
Stateless model checking (SMC) coupled with dynamic
partial order reduction (DPOR) is an effective way for
automatically verifying safety properties of loop-free concurrent
programs. SMC, however, does not work well for programs with
loops because it cannot distinguish loop iterations that make
progress from ones that revisit the same state. This results in
redundant exploration that dominates the verification time.
We present SAVER (Spinloop-Aware Verifier), a memorymodel-
agnostic SMC/DPOR extension that detects zero-net-effect
spinloops and avoids redundant explorations that lead to the same
local state. As confirmed by our experiments, SAVER achieves an
exponential reduction in verification time and outperforms stateof-
the-art tools in a variety of real-world benchmarks.