Formal Verification of Correctness and Information Flow Security for an In-Order Pipelined Processor

Dong, Ning; Guanciale, Roberto; Dam, Mads; Lööw, Andreas

doi:10.34727/2023/isbn.978-3-85448-060-0_33

Record link:

http://hdl.handle.net/20.500.12708/188870
https://doi.org/10.34727/2023/isbn.978-3-85448-060-0_33

Title:

Formal Verification of Correctness and Information Flow Security for an In-Order Pipelined Processor

Citation:

Dong, N., Guanciale, R., Dam, M., & Lööw, A. (2023). Formal Verification of Correctness and Information Flow Security for an In-Order Pipelined Processor. In A. Nadel & K. Y. Rozier (Eds.), Proceedings of the 23rd Conference on Formal Methods in Computer-Aided Design – FMCAD 2023 (pp. 247–256). TU Wien Academic Press. https://doi.org/10.34727/2023/isbn.978-3-85448-060-0_33

reposiTUm DOI:

10.34727/2023/isbn.978-3-85448-060-0_33

CatalogPlus:

AC17203796

Publication Type:

Inproceedings - Full-Paper Contribution

Language:

English

Authors:

Dong, Ning
Guanciale, Roberto
Dam, Mads
Lööw, Andreas

Editors:

Nadel, Alexander
Rozier, Kristin Yvonne