Modeling resource utilization for spiking neural networks in FPGAs

Abstract

Although the concept of machine learning has been around for a long time, to most people it was nothing more than the stuff of science fiction, where rebelling robots threaten to overthrow humanity. Only recently, the introduction of easily accessible technologies (e.g. large language models, image synthesis tools, ...) made a wide public aware of the advantages of utilizing artificial intelligence.Artificial neural networks are mathematical models inspired by the structures and processes observed in the brains of animals. Spiking Neural Networks (SNNs) are a subset focusing on the fact that excitable cells communicate via spikes, encoding information in their timing, rather than transmitting values. While being practically employed less often than other network types, they are very interesting for understanding the nature of intelligent life, because they were invented following groundbreaking studies on modeling the biological brain.The behavior of spiking neural networks can be simulated with general purpose hardware. This is perfectly fine, but as it can be seen in other areas (e.g. rendering, cryptography, ...) systems dedicated to a specific tasks can benefit greatly from hardware accelerators. Purpose-built designs improve performance and energy efficiency, as well as help integrating a specific technology in an otherwise less powerful system.Field-Programmable Gate Arrays (FPGAs) are a type of integrated circuit, containing an array of logic blocks and interconnects, that can be configured to form virtually any digital circuit. They are perfectly suited for evaluating the optimization potential that comes with a dedicated circuit-level design, while having much shorter development and production times.This work will introduce a modular FPGA-based implementation, providing the basic building blocks for constructing networks, and a hardware/software framework for embedding SNNs into real-world applications. Employing the implementation and the framework, we focus on measuring the required hardware resources and resulting performance of different networks, depending on their specific structures. The results will aid in modeling the SNN implementation against different parameters, such as hardware resources and power consumption, allowing the designers to properly select the SNN network structure and the FPGA device. Additionally, such model can aid designers in making a conscious decision when determining whether an FPGA is a viable device for their use-case.Furthermore, we present testing results, in regards to performance, power consumption and resource utilization, based on an example setup, built to classify handwritten digits. The results are in line with our model, with small discrepancies that are further analyzed and discussed, as they are dependent on the occupation and the size of the FPGA device.