Tackling Scalability Issues in Bit-Vector Reasoning

Niemetz, Aina

doi:10.34727/2024/isbn.978-3-85448-065-5_2

Record link:

http://hdl.handle.net/20.500.12708/200769
https://doi.org/10.34727/2024/isbn.978-3-85448-065-5_2

Title:

Tackling Scalability Issues in Bit-Vector Reasoning

Citation:

Niemetz, A. (2024). Tackling Scalability Issues in Bit-Vector Reasoning. In N. Narodytska & P. Rümmer (Eds.), Proceedings of the 24th Conference on Formal Methods in Computer-Aided Design – FMCAD 2024 (pp. 2–2). TU Wien Academic Press. https://doi.org/10.34727/2024/isbn.978-3-85448-065-5_2

reposiTUm DOI:

10.34727/2024/isbn.978-3-85448-065-5_2

CatalogPlus:

AC17313129

Publication Type:

Inproceedings - Full-Paper Contribution

Language:

English

Authors:

Niemetz, Aina

Editors:

Narodytska, Nina
Rümmer, Philipp

Organisational Unit:

E000 - Technische Universität Wien

Series:

Conference Series: Formal Methods in Computer-Aided Design

Published in:

Proceedings of the 24th Conference on Formal Methods in Computer-Aided Design – FMCAD 2024

ISBN:

978-3-85448-065-5

Date (published):

Oct-2024

Number of Pages:

Publisher:

TU Wien Academic Press

Peer reviewed:

Yes

Keywords:

formale Methode; rechnerunterstützte Systementwicklung; Hardwareverifikation; Systemverifikation; formale Verifikation; Spezifikation; Synthese und Testung; automatisches Schlussfolgern; formale Logik

formal methods; computer-aided system design; hardware and system verification; formal verification; specification; synthesis and testing; automated and formal reasoning

Research Areas:

Logic and Computation: 40%
Computer Engineering and Software-Intensive Systems: 40%
Computer Science Foundations: 20%

Science Branch:

1020 - Informatik: 100%

License:

CC BY 4.0