Binary adders are a core component of most digital processing circuitry, and thus much effort has been put forward to optimize them as much as possible, particularly regarding the performance, as measured by the latency of the adder circuitry. However, all of these optimizations are done within the context of a synchronous logic design. Asynchronous logic, in comparison, already has the built-in performance gain of achieving average-case performance, rather than the worst-case performance that synchronous logicis limited by. On the other hand, asynchronous logic requires additional circuitry, such as the Completion Detection (CD), and incurs overheads due to the used encoding for example.This thesis quantitatively analyzes the performance, area usage, and complexity, expressed as the number of nets in the design, of a select group of adder designs, each in a synchronous and an asynchronous variant. These results were obtained by way of simulation using state-of-the-art simulation tools. The designs themselves were implemented in VHDL on the basis of an open cell library. Based on these results extensive comparisons of the noted characteristics were made, which highlight the relative strengths and weaknesses of the implementations.
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