Efficient Multi-Scale Modeling of Semiconductor Device Fabrication

Abstract

In recent years, the traditional transistor scaling has undergone a drastic transition. Instead of a relatively simple shrinking of the planar transistor, the entire geometry has been redesigned. The vertical FinFET is now being followed by a gate-all-around (GAA) transistor design which allows even more electrostatic control of the channel region from the gate bias. It has also become clear that silicon scaling is reaching its end and new materials are being investigated, both for advanced transistor nodes and for a broad range of specialized applications (e.g., wide bandgap semiconductors for power devices). Assessing the feasibility of device fabrication with new materials using experiments alone is very expensive and time-consuming, which is why process simulations are indispensable in today's micro- and nanoelectronics design cycle. In this talk, I will introduce an efficient multi-scale process simulation framework ViennaPS which we are developing to address the needs of modern semiconductor fabrication. Nowadays, it is essential to treat the problem from all scales: From atomistic to the reactor chamber itself.