Record link: 
http://hdl.handle.net/20.500.12708/219560
https://doi.org/10.34727/2025/isbn.978-3-85448-084-6_30
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Title: 
Unlocking Hardware Verification with Oracle Guided Synthesis
en
Citation: 
Ye, L., Li, Y., frankel, guy, Cheng, J., & Polgreen, E. (2025). Unlocking Hardware Verification with Oracle Guided Synthesis. In A. Irfan & D. Kaufmann (Eds.), Proceedings of the 25th Conference on Formal Methods in Computer-Aided Design – FMCAD 2025 (pp. 235–245). TU Wien Academic Press. https://doi.org/10.34727/2025/isbn.978-3-85448-084-6_30
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reposiTUm DOI: 
10.34727/2025/isbn.978-3-85448-084-6_30
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CatalogPlus: 
AC17653248
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Publication Type: 
Inproceedings - Full-Paper Contribution
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Language: 
English
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Authors: 
Ye, Leiqi 
Li, Yixuan 
frankel, guy 
Cheng, Jianyi 
Polgreen, Elizabeth 
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Editors: 
Irfan, Ahmed 
Kaufmann, Daniela 
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Organisational Unit: 
E000 - Technische Universität Wien 
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Series: 
Conference Series: Formal Methods in Computer-Aided Design 
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Published in: 
Proceedings of the 25th Conference on Formal Methods in Computer-Aided Design – FMCAD 2025 
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ISBN: 
978-3-85448-084-6
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Date (published): 
2025
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Number of Pages: 
11
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Publisher: 
TU Wien Academic Press, Wien
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Peer reviewed: 
Yes
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Keywords: 
formal methods; computer-aided system design; hardware and system verification
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Linked records in reposiTUm: has part: 
10.34727/2025/isbn.978-3-85448-084-6
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Research Areas: 
Logic and Computation: 40%
Computer Engineering and Software-Intensive Systems: 40%
Computer Science Foundations: 20%
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Science Branch: 
1020 - Informatik: 100%
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License: 
CC BY 4.0 CC BY 4.0
en
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