Recombination-Driven Interface Trap Generation in SiC MOSFETs Under Constant Voltage and Constant Current Stress

Abstract

We investigate the generation of interface traps during stress at low gate current and moderate gate voltage of SiC MOSFETs. Several stress tests are performed with a custom made, on-wafer, in-situ measurement setup; device degradation is monitored by charge pumping measurements and dc characterization. In essence we observe the following: (i) Ig-Vg curves are dominated by Fowler-Nordheim tunneling up to 8.1 MV/cm at RT; above this threshold, a kink is observed, due to hole generation via impact ionization; (ii) stresses at fields below 8.1 MV/cm result in negligible interface trap generation and moderate threshold voltage shift, due to electron trapping at border states; (iii) stress above 8.1 MV/cm results in a significant generation of interface traps, detected by charge pumping measurements. This interface trap generation is ascribed to the recombination enhanced defect reaction (REDR) caused by the recombination of the holes generated via impact ionization, taking place near the SiO2/SiC interface. Evidence for electron-hole recombination is obtained through electroluminescence investigation.