Timmer, J., Elahi, A., Lehninger, P., & Jantsch, A. (2026). A Low-Resource Hardware Design for Bearing Fault Detection Using Support Vector Machines. IEEE Access, 14, 31316–31326. https://doi.org/10.1109/ACCESS.2026.3666778
E384-02 - Forschungsbereich Systems on Chip E056-10 - Fachbereich SecInt-Secure and Intelligent Human-Centric Digital Technologies E056-16 - Fachbereich SafeSeclab
Bearing fault detection is critical for ensuring the reliability of industrial machinery, as mechanical failures can lead to significant downtime and maintenance costs. This paper presents a hardware-efficient accelerator for bearing fault detection based on Support Vector Machines (SVMs). Unlike neural network–based accelerators, which are often over-parameterized and demand substantial hardware resources, the proposed design focuses on compactness and hardware efficiency. By combining carefully selected time-domain features with quantization and normalization techniques, we developed a hardware-efficient architecture suitable for both FPGA and ASIC implementation. Evaluated on the Case Western Reserve University (CWRU) bearing dataset, the accelerator achieves 96.93% accuracy in the single-variate and 98.42% in the multi-variates implementation. The FPGA implementation and the ASIC synthesized in TSMC 65-nm demonstrate significantly lower hardware requirements compared to state-of-the-art designs, making the proposed approach highly suitable for deployment in resource-constrained environments.
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Research facilities:
Analytical Instrumentation Center
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Project title:
Nanomechanical Hardware Platforms for Edge Computing: 101092018 (European Commission)
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Project (external):
Horizon Europe Horizon Europe
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Project ID:
10061130 10063023
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Research Areas:
Logic and Computation: 60% Mathematical and Algorithmic Foundations: 20% Computer Science Foundations: 20%