Mechanical Reliability of open through silicon via structures for integrated circuits

Abstract

Recently, the semiconductor industry has been investing significant effort towards introducing more functionality to applications beyond memory and logic, referred to as "More-than-Moore" integration. This type of integration, commonly associated with three dimensional (3D) die/wafer stacking, is realized using a through-silicon via (TSV) technology, which allows for a vertical electrical contact between systems, enabling low power consumption, dense device packing, and reduced RC delays. The implementation and fabrication of the 3D structure results in many challenging reliability issues. Therefore, the reliability of every component of the device must be thoroughly analyzed. In this work the reliability related to the mechanical stability of lined (open) TSVs, based on the W metalization technology, is considered. The different aspects which impact the mechanical stability of the TSV interconnects are examined and new models are implemented. The finite element method (FEM) is a numerical method frequently used in semiconductor modeling to support the development of new devices and processes. The mechanical analysis of open TSVs is implemented in a commercial FEM software, where different simulation schemes, materials, and mechanical models are employed. During 3D integrated circuit (IC) stacking devices such as open TSVs can be subjected to unintentional extra forces leading to a failure of the structure. By simulating an external force acting on an open TSV critical areas can be identified, where a mechanical failure is most likely. The highest probability of a failure due to material cracking or delamination is found at the corner of the TSV bottom. Subsequently the critical areas are localized and a delamination analysis is performed for the material interfaces of the multilayer structure at the TSV bottom. Delamination prediction is formulated by using the energy release rate generated during delamination propagation. If the energy release rate exceeds a critical value delamination propagates. Conditions such as the thicknesses of the layers, applied forces, and residual stresses of the involved material layers are varied to investigate which factor increase the probability of delamination propagation. SiO2/W is found to be the most critical interface; when the W layer is assumed to carry a large value of intrinsic tensile stress, high values of energy release rate are obtained. Thin metal films, deposited using complementary metal-oxide-semiconductor (CMOS) fabrication techniques, usually contain residual stresses, which affect the performance and reliability of the IC. High values of intrinsic stress, in particular in the W conducting layer of the open TSV, increase the probability of delamination-induced failure. Therefore, a model is implemented to predict the stress build-up in thin metal film during the deposition process. The model is calibrated by using measured data for several materials and is used to investigate the film stress evolution during film growth on a scalloped surface. During TSV fabrication, due to the deep reactive ion etching process used, a scalloped surface is formed along the TSV sidewall. Thin films grown on a scalloped surface develop a smaller intrinsic stress when compared to flat samples. Therefore, by controlling the process parameters during etching the intrinsic stress in the film can be minimized.