Record link: 
http://hdl.handle.net/20.500.12708/81328
https://doi.org/10.34727/2022/isbn.978-3-85448-053-2_15
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Title: 
Reconciling Verified-Circuit Development and Verilog Development
en
Citation: 
Lööw, A. (2022). Reconciling Verified-Circuit Development and Verilog Development. In A. Griggio & N. Rungta (Eds.), Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022 (pp. 89–98). TU Wien Academic Press. https://doi.org/10.34727/2022/isbn.978-3-85448-053-2_15
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reposiTUm DOI: 
10.34727/2022/isbn.978-3-85448-053-2_15
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Publication Type: 
Konferenzbeitrag - Full-Paper Contribution
de
 
Inproceedings - Full-Paper Contribution
en
Language: 
English
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Authors: 
Lööw, Andreas 
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Editors: 
Griggio, Alberto 
Rungta, Neha 
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Organisational Unit: 
E192-04 - Forschungsbereich Formal Methods in Systems Engineering 
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Series: 
Conference Series: Formal Methods in Computer-Aided Design 
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Published in: 
Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022 
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ISBN: 
978-3-85448-053-2
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Date (published): 
Oct-2022
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Number of Pages: 
10
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Publisher: 
TU Wien Academic Press
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Peer reviewed: 
Yes
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Keywords: 
formale Methode
de
 
formal methods
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Linked records in reposiTUm: has part: 
10.34727/2022/isbn.978-3-85448-053-2
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License: 
CC BY 4.0 CC BY 4.0
en
Appears in Collections:
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Open Access Series

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