Full name Familienname, Vorname
Najvirt, Robert
 
Main Affiliation Organisations­zuordnung
 

Results 1-20 of 21 (Search time: 0.003 seconds).

PreviewAuthor(s)TitleTypeIssue Date
1Tabassam, Zaheer ; Steininger, Andreas ; Najvirt, Robert ; Huemer, Florian ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive LogicInproceedings Konferenzbeitrag 6-Sep-2023
2Behal, Patrick ; Huemer, Florian ; Najvirt, Robert ; Steininger, Andreas ; Tabassam, Zaheer Towards Explaining the Fault Sensitivity of Different QDI Pipeline StylesBeitrag in Tagungsband Inproceedings18-Oct-2021
3Tabassam-2021-InputOutput-Interlocking for Fault Mitigation in QDI Pipelines-am.pdf.jpgTabassam, Zaheer ; Behal, Patrick ; Najvirt, Robert ; Steininger, Andreas Input/Output-Interlocking for Fault Mitigation in QDI PipelinesInproceedings Konferenzbeitrag 2021
4Behal-2021-Towards Explaining the Fault Sensitivity of Different QDI Pipel...-am.pdf.jpgBehal, Patrick ; Huemer, Florian ; Najvirt, Robert ; Tabassam, Zaheer ; Steininger, Andreas Towards Explaining the Fault Sensitivity of Different QDI Pipeline StylesInproceedings Konferenzbeitrag 2021
5Függer, Matthias ; Najvirt, Robert ; Nowak, Thomas ; Schmid, Ulrich A Faithful Binary Circuit ModelArtikel Article 2020
6Huemer-2020-Identification and Confinement of Fault Sensitivity Windows in...-am.pdf.jpgHuemer, Florian Ferdinand ; Najvirt, Robert ; Steininger, Andreas Identification and Confinement of Fault Sensitivity Windows in QDI LogicInproceedings Konferenzbeitrag 2020
7Fuegger Matthias - 2018 - A Faithful Binary Circuit Model with Adversarial Noise.pdf.jpgFügger, Matthias ; Maier, Jürgen ; Najvirt, Robert ; Nowak, Thomas ; Schmid, Ulrich A Faithful Binary Circuit Model with Adversarial NoiseInproceedings Konferenzbeitrag 2018
8Najvirt, Robert ; Polzer, Thomas ; Steininger, Andreas Measuring Metastability with Free-Running ClocksKonferenzbeitrag Inproceedings 2017
9Steininger Andreas - 2016 - Does Cascading Schmitt-Trigger Stages Improve the...pdf.jpgSteininger, Andreas ; Najvirt, Robert ; Maier, Jürgen Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior?Inproceedings Konferenzbeitrag 2016
10Najvirt, Robert ; Függer, Matthias ; Nowak, Thomas ; Schmid, Ulrich ; Hofbauer, Michael ; Schweiger, Kurt Experimental Validation of a Faithful Binary Circuit ModelKonferenzbeitrag Inproceedings 2015
11Függer, Matthias ; Najvirt, Robert ; Nowak, Thomas ; Schmid, Ulrich Towards binary circuit models that faithfully capture physical solvabilityKonferenzbeitrag Inproceedings 2015
12Polzer, Thomas ; Najvirt, Robert ; Beck, Florian ; Steininger, Andreas On the Appropriate Handling of Metastable Voltages in FPGAsArtikel Article 2015
13Najvirt, Robert ; Steininger, Andreas A Pausible Clock with Crystal Oscillator AccuracyKonferenzbeitrag Inproceedings 2015
14Najvirt, Robert ; Steininger, Andreas A Versatile and Reliable Glitch Filter for ClocksKonferenzbeitrag Inproceedings 2015
15Najvirt, Robert ; Steininger, Andreas How to Synchronize a Pausible Clock to a ReferenceKonferenzbeitrag Inproceedings 2015
16Najvirt, Robert ; Polzer, Thomas ; Beck, Florian ; Steininger, Andreas Containment of Metastable Voltages in FPGAsKonferenzbeitrag Inproceedings 2015
17Najvirt, Robert ; Steininger, Andreas Equivalence of clock gating and synchronization with applicability to GALS communicationKonferenzbeitrag Inproceedings 2014
18Lechner, Jakob ; Najvirt, Robert A Generic Architecture for Robust Asynchronous Communication LinksKonferenzbeitrag Inproceedings 2013
19Najvirt, Robert ; Veeravalli, Varadan Savulimedu ; Steininger, Andreas Particle Strikes in C-Gates: Relevance of SET ShapesKonferenzbeitrag Inproceedings 2013
20Najvirt, Robert ; Naqvi, Syed Rameez ; Steininger, Andreas Classifying Virtual Channel Access Control Schemes for Asynchronous NoCsKonferenzbeitrag Inproceedings 2013

Results 1-2 of 2 (Search time: 0.002 seconds).

PreviewAuthor(s)TitleTypeIssue Date
1Ramsl Wolfgang - 2019 - Fault masking in synchronous and in asynchronous logic -...pdf.jpgRamsl, Wolfgang Fault masking in synchronous and in asynchronous logic - a comparsionThesis Hochschulschrift 2019
2Trenkwalder Christian - 2014 - Effekte von Stuck-At Faults in Delay-Insensitiver...pdf.jpgTrenkwalder, Christian Effekte von Stuck-At Faults in Delay-Insensitiver LogikThesis Hochschulschrift 2014