Clock synchronization in a distributed hardware-in-the-loop testbed

Abstract

Power Hardware-in-the-Loop (PHIL) and Controller Hardware-in-the-Loop (CHIL) experiments are valuable for the research and development of novel power-system technologies. In combination with network emulators like CORE (Common Open Research Emulator) complex simulations can be realized with minimal hardware requirements. However, such simulations are quite complex as the number of simultaneous events and generated data grows. Therefore, it is important to provide a common clock by which to timestamp data. For this, accurate timing distribution mechanisms, like the precision time protocol (PTP) IEEE-1588 can be leveraged. The Center for Advanced Power Systems (CAPS) at Florida State University (FSU) is a leader in the field of HIL simulations. Today, the infrastructure at CAPS and partner universities for co-simulation does not include GPS synchronized high precision clock synchronization cross devices used in a HIL experiment. It is, thus, the objective of this master’s thesis to develop a GPS clock synchronization concept for the HIL Testbed. The developed concept will demonstrate the possibility to use that PTP Backbone with different components of a HIL Testbed at CAPS and verify the benefits of a common time base between independent hardware components. This enables the opportunity to measure one-way path delay between two devices in nanosecond resolution. In particular, this method can be used to validate the behavior of emulated networks in CORE compared to real networks. In addition, the resolution of time stamped data from real-time simulators (RTS) can be increased for more precise event determination.