Impact of single-defects on the variability of CMOS inverter circuits

Abstract

Variations in the operational behavior of seemingly identical transistors pose a remarkable challenge for application engineers as integrated circuits have to be designed to be resilient against process and aging-related error sources. In small-area transistors, electrically active defects give rise to considerable device-to-device variations for instance of the threshold voltage. With the ongoing reduction of device dimensions, the impact of a single-defect becomes more and more relevant for the device behavior. While in circuit simulations, typically changes of mean values are considered, we thoroughly investigate the impact of variations of defect distributions on the signal propagation delay of an inverter circuit from the perspective of single oxide and interface defects. For this, the charge trapping kinetics of each defect is described using our stochastic charge trapping model. The impact of these single defects on the device behavior is extracted from detailed experimental studies. We demonstrate that the variation of the defect distributions between devices can lead to a signal propagation delay of several picoseconds for an inverter circuit. This can become a critical issue for circuits employing nanoscale transistors intended to operate at several hundreds of megahertz.