Improved CV characterization technique for interface state evaluation in Si3N4/n-GaN MIS Capacitors

Abstract

Investigating interface defects at dielectrics/III-nitride interface is vital for deeper understanding of threshold voltage shifts in GaN-based MIS or MOS FETs and the dynamic RDS, on in HEMTs. While some researchers use the deviation of the measured capacitance of a stressed curve in relation to an ideal reference curve to quantitatively assess the interface state density, Dit, there is a notable absence of comprehensive discourse regarding the influence of measurement parameters, such as measurement time, on the extraction of the interface density. In this paper, we have established a correlation between the leftward shift in the measured capacitance-voltage (CV) curve, often associated with effects of UV illumination, and the impact of negative bias stress at elevated temperatures, solely attributed to electron emission from trap states. We demonstrate how the extraction of Dit is impacted by the selection of measurement conditions as sampling rates, measurement time and temperature, and we provide a quantitative interpretation of these effects. We demonstrate that the estimation of Dit can be significantly underestimated, by a factor of 4, for extraction times ranging from 70 ms to 200 s, in comparison to previous studies. The technique is applied for Dit extraction at SiN/GaN interface using a MIS-capacitor.