Modeling Non-Uniformity During Two-Step Dry Etching of Si/SiGe Stacks for Gate-All-Around FETs

Abstract

Selective lateral etching of the SiGe layers is one of the most critical steps in Gate-All-Around Field-Effect Transistor (GAAFET) fabrication, which is the basis for the formation of an inner-spacer. Non-uniformity of substrate surface during wet or dry selective etching of SiGe is a common sight in industry, which cannot be modeled using standard process Technology Computer Aided Design (TCAD) approaches. In this paper, we propose a method for the continuous simulation of the two-step dry etching process - anisotropic etching of the Si/SiGe stack and subsequent isotropic selective etching of SiGe - to study the mechanism behind the non-uniform profile formation. The proposed method is able to simulate the non-uniform profile accurately, which was calibrated and verified with experimental data.