Evaluation of the impact of body bias on the threshold voltage drift of planar SiO₂ transistors

Abstract

The performance of semiconductor transistors is significantly influenced by charge trapping at oxide and interface defects. The impact of charge-trapping events of defects on the characteristics of the transistor is strongly dependent on factors such as the geometry and the operating point at which the transistor is used. Understanding the complex relationships between the influence of defects and the robustness of devices is essential to optimize circuit performance and becomes particularly important in analog designs. In this work, we investigate the influence of gate oxide defects on the reliability of nanoscale MOS transistors under varying body bias conditions. Using measure-stress-measure techniques, we observe notable effects on both time-zero and time-dependent variability with the application of body bias. Furthermore, the amplitudes of the step heights are investigated as they provide an important measure in scaled technologies to estimate the impact of traps on the device behavior. The results indicate that a body bias can be strategically employed to enhance device reliability by fine-tuning the body bias conditions.