Electromigration reliability issue in interconnects for three-dimensional integration technologies

Abstract

Innovation in the semiconductor industry has enabled transistor scaling along Moore's law for many decades. More recently, significant effort has been dedicated to the introduction of diversified functionality on a single chip. Attempts to realize this on a single plane results in interconnect congestion as well as increased circuit noise and delay. These issues could be overcome by vertically stacking multiple technologies located on different planes of the chip and providing electrical interconnection by making use of the third dimension. Although interconnect technologies for three-dimensional integration show significant advantages, there are several reliability concerns, as is often the case in emerging technologies. A key reliability issue in modern conducting structures is the influence of electromigration, which is the process of mass-transport-induced failure caused by high current flow in metal lines, on device lifetimes. The prediction of the electromigration lifetime becomes crucial for the assessment of interconnect reliability. Accelerated electromigration testing has been used for decades to determine the factors which affect the lifetime of interconnects, but the mechanisms governing the failure are extremely difficult to identify. The most feasible way is provided by the use of physical modeling. In general, electromigration modeling represents a multiphysics problem which can be divided into two phases, namely, the early phase of void nucleation and the late phase of void evolution. During the first phase, stable voids nucleate in the interconnect due to the development of tensile stress, particularly at those locations where the adhesion between the metal layer and the surrounding material is weak. In turn, the late phase is governed by the void evolution mechanism which leads to extremely high changes in the interconnect resistance until an open circuit failure is noted. The lifetime of the interconnect is found after reaching a maximum resistance value tolerable in the given circuit. The development of the two-phase-model for electromigration and its implementation in a commercial software, based on the finite element method, allows to carry out numerical simulations in an efficient way. In this work, electromigration simulations are performed for realistic interconnect geometries for integration architectures in order to assess their reliability. Case studies of particular interest are open through silicon vias and flip-chip solder bumps. For the first case, electromigration failure is observed to initiate close to the metallization barrier between the via and the adjacent metal level. Once the void has nucleated, its growth is caused by the electromigration-induced-vacancy flux along the void surface. The combination of kinetics of both phases of failure provides a good estimation of the interconnect lifetime. In flip-chip solder bump technologies, electromigration enhances material composition changes which leads to a void nucleation at the bump/intermetallic compound interface. The analysis shows that the solder bump lifetime is dominated by the early phase failure. Furthermore, a newsworthy comparative study regarding the impact of geometry and microstructure on the electromigration failure development in standard interconnect lines is presented. Simulations are capable of reproducing the electromigration phenomenon in diverse structures and ensure meaningful results for the evaluation of their reliability.