Record link: 
http://hdl.handle.net/20.500.12708/196187
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Title: 
Revealing the Impact of Gate Area Scaling on Charge Trapping Employing SiO₂ Transistors
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Citation: 
Tselios, K., Knobloch, T., Waldhör, D., Stampfer, B., Ioannidis, E., Enichlmair, H., Minixhofer, R., Grasser, T., & Waltl, M. (2023). Revealing the Impact of Gate Area Scaling on Charge Trapping Employing SiO₂ Transistors. IEEE Transactions on Device and Materials Reliability, 23(3), 355–362. https://doi.org/10.1109/TDMR.2023.3262141
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Publisher DOI: 
10.1109/TDMR.2023.3262141
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Publication Type: 
Article - Original Research Article
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Language: 
English
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Authors: 
Tselios, Konstantinos 
Knobloch, Theresia 
Waldhör, Dominic 
Stampfer, Bernhard 
Ioannidis , Eleftherios 
Enichlmair , Hubert 
Minixhofer , Rainer 
Grasser, Tibor 
Waltl, Michael 
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Organisational Unit: 
E360 - Institut für Mikroelektronik 
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Journal: 
IEEE Transactions on Device and Materials Reliability 
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ISSN: 
1530-4388
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Date (published): 
Sep-2023
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Number of Pages: 
8
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Publisher: 
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
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Peer reviewed: 
Yes
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Keywords: 
MOSFETs; single defects; charge trapping; positive and negative bias temperature instability (PBTI, NBTI); complementary cumulative distribution function (CCDF); exponential step height distribution; variability
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Research facilities: 
Zentrum für Mikro & Nanostrukturen 
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Project title: 
CD-Labor für Einzeldefektspektroskopie in Halbleiterbauelementen: 00000000 (Christian Doppler Forschungsgesells) 
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Research Areas: 
Materials Characterization: 50%
Nanoelectronics: 50%
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Science Branch: 
2020 - Elektrotechnik, Elektronik, Informationstechnik: 100%
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