Record link: 
http://hdl.handle.net/20.500.12708/226323
-
Title: 
Impact of Charge Trapping at Defects on the Robustness of Electronic Circuits
en
Citation: 
Waltl, M., Stampfer, B., & Lacerda de Orio, R. (2025). Impact of Charge Trapping at Defects on the Robustness of Electronic Circuits. In 2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM 2025), Hong Kong, China. IEEE. https://doi.org/10.1109/EDTM61175.2025.11041458
-
Publisher DOI: 
10.1109/EDTM61175.2025.11041458
-
Publication Type: 
Inproceedings - Full-Paper Contribution
en
Language: 
English
-
Authors: 
Waltl, Michael 
Stampfer, Bernhard 
Lacerda de Orio, Roberto 
-
Organisational Unit: 
E360-01 - Forschungsbereich Mikroelektronik 
-
Published in: 
2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) 
-
Date (published): 
30-Jun-2025
-
Event name: 
9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM 2025) 
en
Event date: 
9-Mar-2025 - 12-Mar-2025
-
Event place: 
Hong Kong, China
-
Number of Pages: 
3
-
Publisher: 
IEEE
-
Peer reviewed: 
Yes
-
Keywords: 
Charge Trapping; Circuit Reliabilty
en
Abstract: 
Charge trapping at oxide defects is a significant reliability issue in MOS transistors and becomes even more prominent in scaled technology nodes. As devices shrink, the impact of charge capture and emission events of oxide and interface defects on performance becomes more severe. Our work demonstrates how charge trapping affects variability in scaled Silicon and 2D technologies, highlighting the necessity of low trap density to achieve high yield and ensure robust electronic circuit designs.
en
Research Areas: 
Materials Characterization: 50%
Modeling and Simulation: 50%
-
Science Branch: 
2020 - Elektrotechnik, Elektronik, Informationstechnik: 100%
-
Appears in Collections:
Conference Paper

Show full item record

Google ScholarTM

Check