Revealing the Impact of Gate Area Scaling on Charge Trapping Employing SiO₂ Transistors

Abstract

The operating characteristics of MOS transistors, such as the switching speed and power consumption, have been improved due to the increased reduction of the lateral dimensions. A further advantage of modern scaled nodes is that defects within the oxide and at the semiconductor/oxide interface are observed in a reduced number, however, they show an enhanced impact on the device characteristics. This leads to a substantially increased variability of the threshold voltages, sub-threshold swing, and carrier mobility when comparing nominally identical devices. As a consequence of this pronounced device-to-device variability, statistical analyses are required for studying the reliability of these technologies. By performing measurements on large sets of devices, statistical distributions of defect properties can be created to study the dependence of statistical quantities, like the link between the average threshold shift of a single emission event and the lateral device dimensions. In this work, the distributions of the contributions of defects on the device behavior are investigated, by making use of commercial pMOS and nMOS devices. The combined use of single-defect extractions and the defect-centric model (DCM) enables us to accurately extract valuable information for a whole technology. While existing approaches focus on either large-area or nanoscale nodes, our results hold for both regimes and are of high relevance for accurately describing the impact of charge traps which is mandatory for further improvement of the layout and performance of circuits.